High-End Drone Computing Architecture Selection Guide: The Technical Logic and Product Options of Pure FPGA vs. MPSoC

In the design of onboard computing architectures for high-end drones, “pure FPGA or MPSoC” is an unavoidable core question. Pure FPGA excels at hardware parallelism and deterministic latency; MPSoC integrates CPU, real-time cores and programmable logic into a single chip, balancing software flexibility and hardware acceleration. The two are not simple substitutes — they correspond to fundamentally different task-load characteristics. As a technical team deeply engaged in the FPGA field, Duyuan Electronics, based on the engineering practice of the ZU19EG and VU13P product lines, sorts out the technical logic of this selection problem from the nature of drone task loads, and provides reference solutions covering different scenarios.

I. Understanding the Heterogeneity of Drone Task Loads

A drone is a typical multi-task real-time system, and its onboard computing requirements can be broadly divided into four categories.

Real-time flight control is the most basic layer. The IMU outputs data at above 1kHz; the flight controller must complete attitude estimation, EKF fusion, attitude-loop and angular-rate-loop control, and update ESCs via PWM or DShot. The whole chain’s cycle is typically within 1ms, and worst-case latency jitter must be strictly bounded.

AI autonomous computing handles target recognition, visual obstacle avoidance, SLAM and path planning. These tasks are compute-intensive but can usually tolerate tens of milliseconds of latency.

Mission payload processing targets video, surveying, inspection and other business data, pursuing throughput rather than extreme real-time performance.

Deterministic signal processing covers radar pulse compression, EW signal processing, high-speed sensor interfaces and time synchronization. Their common characteristic is completion within microseconds with extremely small timing jitter.

These four load types place vastly different demands on chip architecture — and that is the root of the selection problem.

II. Pure FPGA Solution: The Boundary and Value of Determinism

2.1 When to Choose Pure FPGA

The core value of pure FPGA is determinism. Its logic circuits run in hardware parallelism; signal paths are fixed after synthesis and place-and-route, with no OS scheduling, interrupt latency or cache misses. Therefore, FPGAs can deliver nanosecond-level, zero-jitter response.

In radar signal processing, algorithms such as matched filtering, pulse compression and FFT must complete within each pulse period — the FPGA’s hardware pipeline guarantees results within a deterministic number of clock cycles. Electronic warfare is the most representative high-end scenario for pure FPGA. Lockheed Martin, in cooperation with Altera, completed a Gen12 EW transceiver flight demonstration on a Group 2 drone based on the Altera Agilex 9 Direct RF FPGA, achieving detection, identification and geolocation of real emitters in under 12 months while meeting size, weight and power constraints. Agilex 9 Direct RF supports direct RF sampling, eliminating the interface bottleneck between the separate RF front end and the digital processing chain.

Miniaturized radar simulators also rely on FPGAs. The P-band radar target and jammer simulator designed by the 27th Research Institute of China Electronics Technology Group Corporation (CETC) uses an FPGA baseband processing scheme: the whole unit weighs less than 6kg, consumes under 130W, and can generate noise jamming, deceptive jamming and dense false-target signals. For such applications — highly fixed algorithms and extreme latency sensitivity — pure FPGA is almost a rigid choice.

2.2 Engineering Platform for the Pure FPGA Solution

For scenarios demanding extreme determinism such as radar signal processing and electronic warfare, Duyuan Electronics built the VU13P PCIe development board on the AMD Virtex UltraScale+ XCVU13P. The XCVU13P provides 1,728K logic cells, 3,456K registers and 12,288 DSP slices, manufactured on TSMC 16nm FinFET+ process. The board carries 4GB DDR4 (2400 MT/s, 64bit), offering a theoretical bandwidth of approximately 19.2 GB/s. The PCIe Gen3 x16 gold fingers deliver about 15.75 GB/s per direction and roughly 31.5 GB/s bidirectional theoretical bandwidth.

The FMC+ interface provides LA 34 pairs plus HA 24 pairs of differential I/O and 16 pairs of GTY high-speed transceivers, directly connecting high-speed ADC/DAC daughter cards with support for JESD204B and other interface protocols — suitable for building high-channel-count RF signal processing systems. The VU13P’s logic resource scale and high-speed interface density make it an ideal platform for radar pulse compression, EW signal processing and multi-channel high-speed data acquisition.

III. MPSoC Solution: Heterogeneous Integration and Software/Hardware Co-design

3.1 When to Choose MPSoC

The core idea of MPSoC is to cover multiple task types with one chip. Taking the AMD Zynq UltraScale+ MPSoC as an example, it integrates quad-core ARM Cortex-A53 application processors, dual-core Cortex-R5 real-time processors, FPGA programmable logic and DSP modules, interconnected via high-bandwidth AXI buses.

The key advantage of this heterogeneous architecture is task isolation. Safety-critical real-time flight control can run on Cortex-R5 with FreeRTOS or bare-metal programs, guaranteeing deterministic control cycles; AI inference and complex algorithms run Linux on Cortex-A53, enjoying a mature software ecosystem; FPGA logic handles sensor interfaces, data preprocessing and hardware acceleration. All three share on-chip memory and high-speed buses, avoiding the inter-chip communication bandwidth bottleneck and latency of traditional “host plus coprocessor” architectures.

A quantitative comparison comes from Zynq UltraScale+ vs. NVIDIA Jetson TX2: in a 1080p@30fps real-time semantic segmentation overlaid with a PID control loop, the Zynq solution achieved 8ms end-to-end latency versus 22ms for Jetson. The key difference is the 32GB/s AXI bus bandwidth between PS and PL, letting sensor data flow between CPU and FPGA with minimal loss.

Zynq UltraScale+ MPSoC already has mature deployments in drone flight control. Enclustra’s drone flight and video controller uses a ZU-series MPSoC for position control and flight trajectory tracking, with sensors and actuators dynamically reconfigurable through FPGA logic, plus a dual-redundant flight control unit. DJI’s Inspire 2 (released 2016) uses the Zynq XC7Z045 SoC in its CineCore 2.0 imaging system for 4K/60fps real-time video processing — an early landmark application of Zynq in high-end drones.

3.2 Engineering Platform for the MPSoC Solution

For integrated task-computing needs, Duyuan Electronics built the ZU19EG development board on the Zynq UltraScale+ MPSoC XCZU19EG. The ZU19EG belongs to the Zynq UltraScale+ MPSoC EG family; its defining feature is a complete processing system plus large-scale programmable logic integrated on a single chip. The PS side includes quad-core ARM Cortex-A53 application processors (up to 1.5GHz), dual-core Cortex-R5 real-time processors, a Mali-400 GPU, and high-speed peripheral interfaces such as DDR4 controllers, PCIe Gen3, USB 3.0 and Gigabit Ethernet; the PL side provides about 1,143K logic cells, 1,968 DSP slices, 70.6Mb RAM and numerous GTH/GTY high-speed transceivers.

This “software/hardware co-design, dynamic/static combined” heterogeneous architecture can run complex operating systems like Linux while achieving nanosecond-level deterministic response and hardware-level pipeline acceleration through the PL. PS and PL communicate via AXI HP/ACP interfaces, enabling shared-memory architecture and direct register access to hardware accelerators without going through the PCIe protocol stack — typical latency can be controlled within 500ns. The ZU19EG’s overall power consumption is around 30W, far lower than the combination of “FPGA board plus industrial PC”, giving it a significant advantage in space-constrained, cooling-limited embedded environments.

IV. Four Dimensions of Selection Decisions

First, the magnitude of latency requirements. If a task must complete within microseconds with zero jitter — such as radar pulse compression, EW signal processing or high-speed motor control — pure FPGA is the only choice. If the time window is in milliseconds, MPSoC’s real-time cores plus FPGA acceleration are fully capable.

Second, the mutability of algorithms. Scenarios where algorithms, once determined, rarely change are suited to pure FPGA hardware fixation. Scenarios requiring frequent algorithm iteration and rapid verification — such as AI object-detection model updates — favor MPSoC’s software flexibility.

Third, system integration requirements. If the platform has strict SWaP constraints, the MPSoC single-chip solution significantly reduces board area and power. If multi-channel direct RF sampling or ultra-high-speed data acquisition is needed, pure FPGA with an independent RF front end may be more appropriate.

Fourth, functional safety and certification requirements. Aviation-grade drones may need DO-254/DO-178C certification. MPSoC’s heterogeneous architecture naturally supports task isolation — placing safety-critical functions on a dedicated real-time core eases certification compliance. Pure FPGA functional safety design requires a stricter hardware verification process.

V. Recommended Models

MPSoC Direction

AMD Zynq UltraScale+ MPSoC (ZU series) is the most mature MPSoC choice in the drone field. The ZU5EV and ZU7EV integrate quad-core A53, dual-core R5, Mali-400 GPU, H.264/H.265 video codecs and FPGA logic on a single board — suitable as the integrated task-computing platform of high-end drones. The ZU19EG offers higher logic density and DSP resources, suited to simultaneously handling flight control, AI inference and high-speed sensor interfaces. The ZU3EG better fits power- and size-sensitive lightweight solutions, and has been used in research as the onboard computer of indoor-navigation drones.

AMD Versal AI Edge Gen 2 (2VE3858/2VM3858) represents the next-generation evolution direction. It integrates Arm Cortex-A78AE application processors, Cortex-R52 real-time processors, Mali-G78AE GPU, FPGA logic and an AI inference accelerator (AIE-ML v2), delivering over 200k DMIPs of total compute and 2× AI inference performance. New Wave Design has launched the V3211 SOM module based on this chip for drones, loitering munitions and wearable EW applications — its core value is single-chip intelligence: preprocessing, AI inference and post-processing all complete within one chip, reducing dependence on multi-chip solutions.

Microchip PolarFire SoC FPGA has unique advantages in low power and determinism. Its deterministic architecture ensures mission-critical real-time execution, delivering 6500 CoreMarks performance at only about 3W — suitable for power-sensitive high-end drones. Built-in crypto acceleration modules and Trusted Hardware design principles also fit scenarios with strict firmware integrity and data security requirements.

Pure FPGA Direction

Altera Agilex 9 Direct RF series is the flagship choice for EW and radar applications. Devices such as the AGRW039 support direct RF sampling rates up to 64Gsps, integrating high-speed ADC/DAC and FPGA logic and eliminating the separate RF front end. Lockheed Martin’s SWIFT program has proven its operational capability on Group 2 drones.

AMD Virtex UltraScale+ VU13P/VU9P offer extremely high logic density and high-speed interfaces. The VU13P has millions of logic cells, numerous DSP slices and high-speed GTY transceivers, suited to radar pulse compression, EW signal processing and multi-channel high-speed data acquisition. FMC+ interfaces connect high-speed ADC/DAC daughter cards with JESD204B and other protocol support.

AMD Kintex UltraScale+ XQRKU060 represents the radiation-hardened direction, supporting unlimited in-orbit reconfiguration — suitable for drones or near-space platforms in high-radiation environments.

VI. Typical Configuration Solutions Based on the Duyuan Electronics Platform

Solution 1: Integrated Task-Computing Platform (MPSoC-oriented)

With the ZU19EG development board as the core: the PS side runs Linux + PX4/ROS 2, the Cortex-R5 cores run safety-critical attitude control, and the PL side implements sensor preprocessing and AI inference acceleration. Suitable for medium-to-large drones that simultaneously handle flight control, visual navigation and target recognition. Duyuan Electronics provides a one-stop full-stack FPGA solution for this platform — from hardware design, logic development and IP core customization to embedded software development — helping teams quickly complete the full process from selection verification to prototype deployment.

Solution 2: Dedicated Signal Processing Platform (Pure FPGA)

With the VU13P development board as the core, connect high-speed ADC/DAC daughter cards through FMC+ interfaces to build a radar or EW signal processing system. The VU13P’s 1,728K logic cells and 12,288 DSP slices are sufficient to implement hardware pipelines for multi-channel pulse compression, FFT and matched filtering. Suitable for military or special-purpose drone missions with extreme deterministic latency requirements.

Solution 3: Heterogeneous Co-design Architecture (MPSoC + Independent FPGA)

Use the ZU19EG as the main control computing platform, connecting the VU13P via PCIe Gen3 x16 or high-speed GTY links as a dedicated coprocessor. The ZU19EG handles flight control, mission management and system scheduling, while the VU13P handles real-time signal processing at the radar or EW front end. This division combines software ecosystem with hardware determinism — a common form of today’s highest-end drone computing architectures.

Conclusion

The answer to “pure FPGA or MPSoC” does not lie in which chip is inherently better, but in the tension between the determinism requirements of task loads and algorithm mutability. Pure FPGA is irreplaceable for microsecond-level determinism and dedicated signal processing; MPSoC holds the advantage in system integration, software flexibility and multi-task isolation. High-end drone architecture design is essentially about letting each class of computing task land on the hardware best suited to it: real-time flight control tasks run on Cortex-R5 cores, AI inference runs on Cortex-A53 with FPGA acceleration, and radar signal processing completes in pure FPGA hardware pipelines.

With the ZU19EG and VU13P product lines covering the complete technical spectrum from MPSoC to pure FPGA, Duyuan Electronics, together with its one-stop full-stack FPGA solution, provides end-to-end support — from chip to system — for the selection verification and engineering implementation of high-end drone computing architectures.